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LH28F008SA
FEATURES
40-PIN TSOP
8M (1M x 8) Flash Memory
TOP VIEW
* Very High-Performance Read
- 85 ns Maximum Access Time
A19 A18 A17 A16 A15 A14 A13 A12 CE VCC VPP PWD A11 A10 A9 A8 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3
* High-Density Symmetrically Blocked
Architecture - Sixteen 64K Blocks
* Extended Cycling Capability
- 100,000 Block Erase Cycles - 1.6 Million Block Erase Cycles per Chip
* Automated Byte Write and Block Erase
- Command User Interface - Status Register
* System Performance Enhancements
- RY/BY Status Output - Erase Suspend Capability
* Deep-Powerdown Mode
- 0.20 A ICC Typical
* SRAM-Compatible Write Interface * Hardware Data Protection Feature
- Erase/Write Lockout during Power Transitions
28F008SA-1
* Independent Software Vendor Support
- Microsoft Flash File SystemTM (FFS)
Figure 1. 40-Pin TSOP Configuration
* ETOXTM Nonvolatile Flash Technology
- 12 V Byte Write/Block Erase
* Industry Standard Packaging
- 40-Pin 1.2 mm x 10 mm x 20 mm TSOP (Type I) Package - 44-Pin 600-mil SOP Package
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LH28F008SA
8M (1M x 8) Flash Memory
44-PIN SOP VPP RP A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE OE RY/BY DQ7 DQ6 DQ5 DQ4 VCC
TOP VIEW
The LH28F008SA is offered in 40-pin TSOP (standard) package. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The LH28F008SA memory map consists of 16 separately erasable 64K blocks. SHARP's LH28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media. A deep powerdown mode lowers power consumption to 1 W typical through VCC, crucial in portable computing, handheld instrumentation and other low-power applications. The PWD power control input also provides absolute data protection during system power up/down.
DESCRIPTION
The LH28F008SA is a high-performance 8M (8,388,608 bit) memory organized at 1M (1,048,576 bytes) of 8 bits each. Sixteen 64K (65,536 Byte) blocks are included on the LH28F008SA. A memory map is shown in Figure 4 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can be independently erased and written 100,000 cyles. Erase Suspend mode allows system software to suspend block erase to read data or execute code from any other block of the LH28F008SA. The LH28F008SA is available in the 40-pin TSOP (Thin Small Outline Package, 1.2 mm thick) package. Pinouts are shown in Figure 1 of this specification. The Command User Interface serves as the interface between the microprocessor or microcontroller and the internal operation of the LH28F008SA. Byte Write and Block Erase Automation allow byte write and block erase operations to be executed using a two-write command sequence to the Command User Interface. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in byte increments typically within 9 s, an 80% improvement over current flash memory products. IPP byte write and block erase currents are 10 mA typical, 30 mA maximum. VPP byte write and block erase voltage is 11.4 V to 12.5 V. The Status Register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation.
28F008SA-16
Figure 2. 44-Pin SOP Configuration
INTRODUCTION
SHARP'S LH28F008SA 8M Flash FileTM Memory is the highest density nonvolatile read/write solution for solid state storage. The LH28F008SA's extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The LH28F008SA brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on rapid execute-in-place and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases relaibility by reducing disk drive accesses. For high density data acquisition applications, the LH28F008SA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can take advantage of the LH28F008SA's nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs.
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8M (1M x 8) Flash Memory
LH28F008SA
DQ0 - DQ7
OUTPUT BUFFER
INPUT BUFFER
IDENTIFIER REGISTER OUTPUT MULTIPLEXER STATUS REGISTER DATA REGISTER
I/O LOGIC
DATA COMPARATOR
COMMAND USER INTERFACE
CE WE OE PWD
A0 - A19
INPUT BUFFER Y-DECODER ADDRESS LATCH X-DECODER ADDRESS COUNTER
Y-GATING
WRITE STATE MACHINE
RY/BY
16 64KB BLOCKS
PROGRAM/ ERASE VOLTAGE SWITCH
Figure 3. LH28F008SA Block Diagram
...
VPP
VCC GND
28F008SA-2
3
LH28F008SA
8M (1M x 8) Flash Memory
PIN DESCRIPTION
SYMBOL TYPE NAME AND FUNCTION ADDRESS INPUTS: For memory addresses. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during Command User Interface write cycles; outputs data during memory array. Status Register and Identifier read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic input buffers, decoders, and sense amplifiers. CE is active low: CE high deselects the memory device and reduces power consumption to standby levels. POWERDOWN: Puts the device in deep powerdown mode. PWD is active low; PWD high gates normal operation. PWD also locks out block erase or byte write operations when active low, providing data protection during power transitions. OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle. OE is active low. WRITE ENABLE: Controls writes to the Command User Interface and array blocks. WE is active low. Addresses and data are latched on the rising edge of the WE Pulse. READY/BUSY: Indicates the status of the internal Write State Machine. When low, it indicates that the WSM is performing a block erase or byte write operation. RY/BY high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep powerdown mode. RY /BY is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled. BLOCK ERASE/BYTE WRITE POWER SUPPLY: for erasing blocks of the array or writing bytes of each block. NOTE: With VPP < VPPLMAX, memory contents cannot be altered. DEVICE POWER SUPPLY: (5 V 10%, 5 V 5%)
A0 - A19
INPUT
DQ0 - DQ7
INPUT/OUTPUT
CE
INPUT
PWD
INPUT
OE
INPUT
WE
INPUT
RY /BY
OUTPUT
VPP VCC GND
SUPPLY
SUPPLY
GROUND
4
8M (1M x 8) Flash Memory
LH28F008SA
The RY/BY output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY minimizes both CPU overhead and system power consumption. When low, RY/BY indicates that the WSM is performing a block erase or byte write operation. RY/BY high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep power down mode. Maximum access time is 85 ns (tACC) over the commercial temperature range (0C to +70C) and over VCC supply voltage range (4.5 V to 5.5 V and 4.75 V to 5.25 V). ICC active current (CMOS Read) is 20 mA typical, 35 mA maximum at 8 MHz. When the CE and PWD pins are at VCC, the ICC CMOS Standby mode is enabled. A Deep Powerdown mode is enabled when the PWD pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power down is 0.20 A typical. Reset time of 400 ns is required from PWD switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 s from PWD high until writes to the Command User Interface are recognized by the LH28F008SA. With PWD at GND, the WSM is reset and the Status Register is cleared.
MEMORY MAP
FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK 64KB BLOCK
PRINCIPLES OF OPERATION
The LH28F008SA includes on-chip write automation to manage write and erase functions. The Write State Machine allows for 100% TTL-level control inputs; fixed power supplies during block erasure and byte write; and minimal processor overhead with SRAM like interface timings. After initial device powerup, or after return from deep powerdown mode (see Bus Operations), the LH28F008SA functions as a read-only memory. Manipulation of external memory-control pins allow array read, standby and output disable operations. Both Status Register and intelligent identifiers can also be accessed through the Command User Interface when VPP = VPPL. This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful block erasure and byte writing of the device. All functions associated with altering memory contents - byte write, block erase, status and intelligent identifier - are accessed via the Command User Interface and verified through the Status Register.
28F008SA-4
Figure 4. Memory Map
Commands are written using standard microprocessor write timings. Command User Interface contents serve as input to the WSM, which controls the block erase and byte write circuitry. Write cycles also internally latch addresses and data needed for byte write or block erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output byte write and block erase status for verification.
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LH28F008SA
8M (1M x 8) Flash Memory
SA0 - SA16 LA17 - LA20
12 V SA1 - SA16 LA17 - LA20 LATCH SA0 LA21 - LA22 SBHE A0 - A19 CSL1 CSH1 LH28F008SA CE CE LH28F008SA VPP WE A0 - A19 VPP SWITCH GPIO RESET
SBHE PSTART PCMD 80386SL PM/IO PW/R FLSHDCS PRDY VGACS
CS TO OTHER LH28F008SA's PLD WR RD CS1 CS2 RY/BY CTRL CS3 WE OE
VPP
OE
DQ0 - DQ7
SD0 - SD15
XCVR FD0 - FD7 FD8 - FD15
82360SL CONTROLLER
INT
RY/BY RESET
PWRGOOD RD WR RY/BY1 RY/BY2 EPLD(s) RY/BY FROM OTHER LH28F008SA's PWD PWD TO OTHER LH28F008SA PAIRS
28F008SA-3
Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus (Including RY/BY Masking and Selective Powerdown), for DRAM Backup during System SUSPEND, Resident O/S and Applications and Motherboard Solid-State Disk.
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DQ0 - DQ7
RY/BY
PWD
8M (1M x 8) Flash Memory
LH28F008SA
Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the LH28F008SA blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of byte write and/or block erase, code/data reads from the LH28F008SA are again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase to read data and execute code from any other block.
Data Protection
Depending on the application, the system designer may choose to make the VPP power switchable (available only when memory byte writes/block erases are required) or hardwired to VPPH. When VPP = VPPL, memory contents cannot be altered. The LH28F008SA Command User interface architecture provides protection from unwanted byte write or block erase operations even when high voltage is applied to VPP. Additionally, all functions are disabled whenever VCC is below the write lockout voltage VLKO, or when PWD is at VIL. The LH28F008SA accomodates either design practice and encourages optimization of the processormemory interface. The two-step byte write/block erase Command User Interface write sequence provides additional software write protection.
Command User Interface and Write Automation
An on-chip state machine controls block erase and byte write, freeing the system processor for other tasks. After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the Status Register and RY/BY output. Byte write is similarly controlled, after destination address and expected data are supplied. The program and erase algorithms of past standard Flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data.
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Read
The LH28F008SA has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or Status Register. VPP can be at either VPPL or VPPH.
Bus Operations
MODE PWD CE OE WE A0 VPP DQ0 - DQ7 RY /BY NOTE
Read Output Disable Standby Deep Power Down Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write
VIH VIH VIH VIL VIH VIH VIH
VIL VIL VIH X VIL VIL VIL
VIL VIH X X VIL VIL VIH
VIH VIH X X VIH VIH VIL
X X X X VIL VIH X
X X X X X X X
DOUT High-Z High-Z High-Z 89H A2H DIN
X X X VOH VOH VOH X
1, 2, 3 3 3
3, 4, 5
NOTES: 1. Refer to DC Characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages. 3. RY/BY is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is V OH when the WSM is not busy, in Erase Suspend mode or deep powerdown mode. 4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH. 5. Refer to the Command Definitions Table for valid DIN during a write operation.
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LH28F008SA
8M (1M x 8) Flash Memory
The first task is to write the appropriate read mode command to the Command User Interface (array, intelligent identifier, or Status Register). The LH28F008SA automatically resets to Read Array mode upon initial device powerup or after exit from deep powerdown. The LH28F008SA has four control pins, two of which must be logically active to obtain data at the outputs. Chip Enable (CE) is the device selection control, and when active enables the selected memory device. Output Enable (OE) is the data input/output (DQ0 - DQ7) direction control, and when active drives data from the selected memory onto the I/O bus. PWD and WE must also be at VIH. Figure 8 illustrates read bus cycle waveforms.
the status of OE. If the LH28F008SA is deselected dur ing block erase or byte write, the device will continue functioning and consuming normal active power until the operation completes.
Deep Power-Down
The LH28F008SA offers a deep power-down feature, entered when PWD is at VIL. Current draw through VCC is 0.20 A typical in deep powerdown mode, with current draw through VPP typically 0.1 A. During read modes, PWD-low deselects the memory, places output drivers in a high-impedence state and turns off all internal circuits. The LH28F008SA requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from powerdown until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The Command User interface is reset to Read Array, and the upper 5 bits of the Status Register are cleared to value 100,000, upon return to normal operation. During block erase or byte write modes, PWD low will abort either operation. Memory contents of the block being altered are no longer valid as the data will be partially written or erased. Time tPHWL after PWD goes to logic-high (VIH) is required before another command can be written.
Output Disable
With OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 - DQ7) are placed in a high-impedance state.
Standby
CE at a logic-high level (VIH) places the LH28F008SA in standby mode. Standby operation disables much of the LH28F008SA's circuitry and substantially reduces device power consumption. The outputs (DQ0 - DQ7) are placed in a high-impedance state independent of
Command Definitions
COMMAND BUS CYCLES REQ'D FIRST BUS CYCLE OPER. ADDRESS DATA SECOND BUS CYCLE NOTE OPER. ADDRESS DATA
Read Array/Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup/Erase Confirm Erase Suspend/Erase Resume Byte Write Setup/Write Alternate Byte Write Setup/Write
1 3 2 1 2 2 2 2
Write Write Write Write Write Write Write Write
X X X X BA X WA WA
FFH 90H 70H 50H 20H B0H 40H 10H Write Write Write Write BA X WD WD D0H D0H WD WD Read Read IA X IID SRD
1 2, 3, 4 3
2
2, 3, 5 2, 3, 5
NOTES: 1. Bus operations are defined in Bus Operations Table. 2. IA = Identifier Address: D0H for manufacturer code, 01H for device code. BA = Address within the block being erased. WA = Address of memory location to be written. 3. SRD = Data read from Status Register. See Status Register Definitions Table for a description of the Status Register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE. IID = Data read from intelligent identifiers. 4. Following the intelligent identifier command, two read operations access manufacture and device codes. 5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command. 6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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8M (1M x 8) Flash Memory
LH28F008SA
Intelligent Identifier Operation
The intelligent identifier operation outputs the manufacturer code 89H; and the device code, A2H for the LH28F008SA. The system CPU can then automatically match the device with its proper block erase and byte write algorithms. The manufacturer and device-codes are read via the Command User Interface. Following a write of 90H to the Command User Interface, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the device code (A2H). It is not necessary to have high voltage applied to VPP to read the intelligent identifiers from the Command User Interface.
data information needed to execute the command. Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Byte Write Setup command requires both appropriate command data and the address of the location to be written, while the Byte Write command consists of the data to be written and the address of the location to be written. The Command User Interface is written by bringing WE to a logic-low level (VIL) while CE is low. Addresses and data are latched on the rising edge of WE. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the AC Waveforms for Write Operations, Figure 9, for specific timing parameters.
Write
Writes to the Command User Interface enable reading of device data and intelligent identifiers. They also control inspection and clearing of the Status Register. Additionally, when VPP = VPPH, the Command User Interface controls block erasure and byte write. The contents of the interface register serve as input to the internal state machine. The Command User Interface itself does not occupy an addressable memory location. The interface register is a latch used to store the command and address and
COMMAND DEFINITIONS
When VPPL is applied to the VPP pin, read operations from the Status Register, intelligent identifiers, or array blocks are enabled. Placing VPPH on VPP enables successful byte write and block erase operations as well. Device operations are selected by writing specific commands into the Command User Interface. Command Definitions Table defines the LH28F008SA commands.
Status Register Definitions
WSMS 7 ESS 6 ES 5 BWS 4 VPPS 3 R 2 R 1 R 0
SR.7
= WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase in Progress/Completed = ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful Block Erase = BYTE WRITE STATUS (BWS) 1 = Error in Byte Write 0 = Successful Byte Write = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK
NOTES: 1. RY/BY or the Write State Machine Status bit must first be checked to determine byte write or block erase operation, before the Byte Write or Erase Status bit are checked to success. 2. If the Byte Write AND Erase Status bits are set to '1's during a block erase attempt, an improper command sequence was entered. Attempt the operation again. 3. If VPP low status is detected, the Status Register must be cleared before another byte write or block erase operation is attempted. The VPP Status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP Status bit is not gauranteed to report accurate feedback between VPPL and VPPH. 4. SR.2 - SR.0 = Reserved for future enhancements. These bits are reserved for future use and should be masked out when polling the Status Register.
SR.6
SR.5
SR.4
SR.3
9
LH28F008SA
8M (1M x 8) Flash Memory
Read Array Command
Upon initial device powerup and after exit from deep powerdown mode, the LH28F008SA defaults to Read Array mode. This operation is also initiated by writing FFH into the Command User Interface. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the Command User Interface contents are altered. Once the internal Write State Machine has started a block erase or byte write operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when VPP = VPPL or VPPH.
Additionally, the VPP Status bit (SR.3) MUST be reset by system software before further byte writes or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the Command User Interface. The Clear Status Register command is functional when VPP = VPPL or VPPH.
Erase Setup/Erase Confirm Commands
Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the Command User Interface, followed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After the two-command erase sequence is written to it, the LH28F008SA automatically outputs Status Register data when read (see Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY/BY pin, or the WSM Status bit of the Status Register. When erase is completed, the Erase Status bit should be checked. If erase error is detected, the Status Register should be cleared. The Command User Interface remains in Read Status Register mode until further commands are issued to it. This two-step sequence of set-up followed by execution insures that memory contents are not accidentially erased. Also, reliable block erasure can only occur when VPP = VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while VPP = VPPL, the VPP Status bit will be set to '1'. Erase attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted.
Intelligent Identifier Command
The LH28F008SA contains an intelligent identifier operation, initiated by writing 90H into the Command User Interface. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the intelligent identifier command is functional when VPP = VPPL or VPPH.
Read Status Register Command
The LH28F008SA contains a Status Register which may be read to determine when a byte write or block erase operation is complete, and whether that operation completed successfully. The Status Register may be read at any time by writing the Read Status Register command (70H) to the Command User Interface. After writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command User Interface. The contents of the Status Register are latched on the falling edge of OE or CE, whichever occurs last in the read cycle. OE or CE must to toggled to VIH before further reads to update the Status Register latch. The Read Status Register command functions when VPP = VPPL or VPPH.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the Erase Suspend command (B0H) to the Command User Interface requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The LH28F008SA continues to output Status Register data when read, after the Erase Suspend command is written to it. Polling the WSM Status and Erase Suspend Status bits will determined when the erase operation has been suspended (both will be set to '1'). RY/BY will also transition to VOH.
Clear Status Register Command
The Erase Status and Byte Write Status bits are set to '1's by the Write State Machine and can only be reset by the Clear Status Register Command. These bits indicate various failure conditions (see Status Register Definitions). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The Status Register may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way the device may be used.
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8M (1M x 8) Flash Memory
LH28F008SA
At this point, a Read Array command can be written to the Command User Interface to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process. The Erase Suspend Status and WSM Status bits of the Status Register will be automatically cleared and RY/BY will return to VOL. After the Erase Resume command is written to it, the LH28F008SA automatically outputs Status Register data when read (see Erase Suspend/Resume Flowchart). V PP must remain at V PPH while the LH28F008SA is in Erase Suspend.
AUTOMATED BYTE WRITE
The LH28F008SA integrates the Quick-Pulse programming algorithm using the Command User Interface, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and provides processor interface timings to the Command User Interface and Status Register. WSM operation, internal verifyand V PP high voltage presence are monitored and reported via the RY/BY output and appropriate Status Register bits. Figure 5 shows a system software flowchart for device byte write. The entire sequence is performed with VPP at VPPH. Byte write abort occurs when PWD transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially written at the location where byte write aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value.
Byte Write Setup/Write Commands
Byte write is executed by a two-command sequence. The Byte Write Setup command (40H) is written to the Command User Interface, followed by a second write specifying the address and data (latched on the rising edge of WE) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two-command byte write sequence is written to it, the LH28F008SA automatically outputs Status Register data when read (see Byte Write Flowchart). The CPU can detect the completion of the byte write event by analyzing the output of the RY/BY pin, or the WSM Status bit of the Status Register. Only the Read Status Register command is valid while byte write is active. When byte write is complete, the Byte Write Status bit should be checked. If byte write error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for '1's that do not successfully write to '0's. The Command User Interface remains in Read Status Register mode until further commands are issued to it. If byte write is attempted while VPP = VPPL, the VPP Status bit will be set to '1'. Byte write attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted.
AUTOMATED BLOCK ERASE
As above, the Quick-Erase algorithm is now implemented internally, including all preconditioning of block data. WSM operation, erase success and VPP high voltage presence are monitored and reported through RY/BY and the Status Register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase Status and Byte Write Status bits will be set to '1's. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 6 shows a system software flowchart for block erase. Erase typically takes 1.6 seconds per block. The Erase Suspend/Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 7. The entire sequence is performed with VPP at VPPH. Abort occurs when PWD transitions to VIL or VPP fails to VPPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block.
EXTENDED BLOCK ERASE/BYTE WRITE CYCLING
The LH28F008SA is designed for 100,000 byte write/ block erase cycles on each of the sixteen 64K blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the tunneling electric field combine to greatly reduce oxide stress and the probability of failure. A 20M solid-state drive using an array of LH28F008SAs has a MTBF (Mean Time Between Failure) of 33.3 million hours(1), over 600 times more reliable than equivalent rotating disk technology.
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LH28F008SA
8M (1M x 8) Flash Memory
DESIGN CONSIDERATIONS Three-Line Output Control
The LH28F008SA will often be used in large memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Three-line control provides for:
ally, for every 8 devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between V CC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
VPP Trace on Printed Circuit Boards
Writing flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP Supply traces and decoupling will decrease VPP voltage spikes and overshoots.
* Lowest possible memory power dissipation * Complete assurance that data bus contention will
not occur To efficiently use these control input, an address decoder should enable CE, while OE should be connected to all memory devices and the system's READ control line. This assures that only selected memory devices have active outputs while deselected memory devices are in Standby Mode. Finally, PWD should either be tied to the system RESET, or connected to VCC if unused.
NOTE: 1. Assumptions: 10K file written every 10 minutes. (20M array 10K file) = 2,000 file writes before erase required. (2000 files writes/erase) x (100,000 cycles per LH28F008SA block) = 200 million file writes. (200 x 106 file writes) x 10 minutes/write) x 1 hr/60 minutes) = 33.3 x 102 MTBF.
VCC, VPP, PWD Transitions and the Command/Status Registers
Byte write and block erase completion are not guaranteed if VPP drops below VPPH. If the VPP Status bit of the Status Register (SR.3) is set to '1', a Clear Status Register command MUST be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the Byte Write (SR.4) or Erase (SR.5) Status bits of the Status Register will be set to '1's if error is detected. PWD transitions to VIL during byte write and block erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device poweroff, or PWD transitions to VIL, clear the Status Register to initial value 10,000 for the upper 5 bits. The Command User Interface latches commands as issued by system software and is not altered by VPP or CE transitions or WSM actions. Its state upon power up, after exit from deep powerdown or after VCC transitions below VLKO, is Read Array Mode. After byte write or block erase is complete, even after VPP transitions down to VPPL, the Command User Interface must be reset to Read Array mode via the Read Array command if access to the memory array is desired.
RY/BY and Byte Write/Block Erase Polling
RY/BY is a full CMOS output that provides a hardware method of detecting byte write and block erase completion. It transitions low time tWHRL after a write or erase command sequence is written to the LH28F008SA, and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY can be connected to the interrupt input of the system CPU or controller. It is active at all times, not instated if the LH28F008SA CE or OE inputs are brought to VIH. RY/BY is also VOH when the device is in Erase Suspend or deep powerdown modes.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in 3 supply current issues: standby current levels (ISB), active current levels (ICC) and transient peaks produced by falling and rising edges of CE. Tran sient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will supress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to package leads. Addition-
Power Up/Down Protection
The LH28F008SA is designed to offer protection against accidental block erasure or byte writing during power transitions. Upon power-up, the LH28F008SA is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the LH28F008SA ensures that the Command User Interface is reset to the Read Array mode on power up.
12
8M (1M x 8) Flash Memory
LH28F008SA
START
BUS OPERATION
COMMAND
COMMENTS
WRITE 40H (10H), BYTE ADDRESS
Write
Byte Write Setup Byte Write
Data = 40H (10H) Addr = Byte to be written Data to be written Addr = Byte to be written Check RY/BY VOH = Ready, VOL = Busy or Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to update Status Register
Write
WRITE BYTE ADDRESS/DATA
Standby/Read
WSM READY?
NO
YES FULL STATUS CHECK IF DESIRED
Repeat for subsequent bytes. Full status check can be done after each byte or after a sequence of bytes.
BYTE WRITE COMPLETED
Write FFH after the last byte write operation to reset the device to Read Array Mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA READ (see above) BUS OPERATION
COMMAND
COMMENTS
Optional Read
SR.3 = 0 ? YES NO VPP RANGE ERROR
CPU may already have read Status Register data in WSM Ready polling above Check SR.3 1 = VPP Low Detect Check SR.4 1 = Byte Write Error
Standby Standby
SR.4 = 0 ? YES
NO
BYTE WRITE ERROR
SR.3 must be cleared, if set during a byte write attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the Clear Status Register Command, in cases where multiple bytes are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
28F008SA-5
BYTE WRITE SUCCESSFUL
Figure 5. Automated Byte Write Flowchart
13
LH28F008SA
8M (1M x 8) Flash Memory
START
BUS OPERATION
COMMAND
COMMENTS
Write
WRITE 20H BLOCK ADDRESS
Erase Setup Erase
Data = 20H Addr = Within block to be erased Data = D0H Addr = Within block to be erased Check RY/BY VOH = Ready, VOL = Busy or Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to update Status Register
Write
WRITE D0H BLOCK ADDRESS
Standby/Read
NO WSM READY? ERASE SUSPEND LOOP YES
NO
SUSPEND ERASE?
YES FULL STATUS CHECK IF DESIRED
Repeat for subsequent bytes. Full status check can be done after each block or after a sequence of blocks.
BLOCK ERASE COMPLETED
Write FFH after the last block erase operation to reset the device to Read Array Mode.
FULL STATUS CHECK PROCEDURE
STATUS REGISTER DATA READ (see above) BUS OPERATION COMMAND COMMENTS
Optional Read Standby
VPP RANGE ERROR
CPU may already have read Status Register data in WSM Ready polling above Check SR.3 1 = VPP Low Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
SR.3 = 0 ? YES
NO
Standby
SR.4, 5 = 1 ? NO
YES
COMMAND SEQUENCE ERROR
Standby
SR.3 must be cleared, if set during a block erase attempt, before further attempts are allowed by the Write State Machine.
NO BLOCK ERASE ERROR
SR.5 = 0 ? YES
SR.5 is only cleared by the Clear Status Register Command, in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
BLOCK ERASE SUCCESSFUL
28F008SA-6
Figure 6. Automated Block Erase Flowchart
14
8M (1M x 8) Flash Memory
LH28F008SA
START
BUS OPERATION
COMMAND
COMMENTS
WRITE B0H
Write Write
Erase Suspend Read Status Register
Data = B0H Data = 70H
WRITE 70H
Standby/Read
READ STATUS REGISTER
Check RY/BY VOH = Ready, VOL = Busy or Read Status Register Check SR.7 1 = Ready, 0 = Busy Toggle OE or CE to Update Status Register
SR.7 = 1 ? YES
NO
Standby Write
SR.6 = 1 ? YES WRITE FFH NO
Check SR.6 1 = Suspended Read Array Data = FFH Read array data from block other than that being erased. Erase Resume Data = D0H
Read
ERASE HAS COMPLETED
Write
DONE READING ? YES WRITE D0H
NO
CONTINUE ERASE
28F008SA-7
Figure 7. Erase Suspend/Erase Resume Flowchart A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE and CE must be low for a command write, driving either to VIH will inhibit writes. The Command User Interface architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-setup command sequences. Finally, the device is disabled until PWD is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life, because the LH28F008SA does not consume any power to retain code or data when the system is off. In addition, the LH28F008SA's deep powerdown mode ensures extremely low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an array of LH28F008SAs for solid-state storage, can lower PWD to VIL in standby or sleep modes, producing negligible power consumption. If access to the LH28F008SA is again needed, the part can again be read, following the tPHQV and tPHWL wakeup cycles required after PWD is first raised back to VIH. See AC Characteristics - ReadOnly and Write Operations and Figures 8 and 9 for more information.
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during
15
LH28F008SA
8M (1M x 8) Flash Memory
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature During Read ......................................... 0C to +70C1 During Block Erase/Byte Write ............... 0C to +70C Temperature Under Bias ..................... -10C to +80C Storage Temperature ......................... -65C to +125C Voltage on Any Pin (except VCC and VPP) with Respect to GND ..................... -2.0 V to +7.0 V2 VPP Program Voltage with Respect to GND during Block Erase/Byte Write .............-2.0 V to +14.0 V2, 3 VCC Supply Voltage with Respect to GND ........................................... -2.0 V to +7.0 V2 Output Short Circuit Current .......................... 100 mA4
*WARNING: Stressing the device beyond
the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
OPERATING CONDITIONS
SYMBOL PARAMETER MIN. MAX. UNITS NOTE
TA VCC VCC
Operating Temperature VCC Supply Voltage (10%) VCC Supply Voltage (5%)
0 4.50 4.75
70.0 5.50 5.25
C V V 5 5
NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods < 20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. 5% VCC specification reference the LH28F008SA-85 in its High Speed configuration, 10% V CC specifications reference the LH28F008SA-85 in its Standard configuration, and the LH28F008SA-12.
DC CHARACTERISTICS
SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE
ILI ILO
Input Load Current Output Leakage Current 1.0
1.0 10.0 2.0 100.0 1.2
A A mA A A
VCC = VCC MAX., VIN = VCC or GND VCC = VCC MAX., VOUT = VCC or GND VCC = VCC MAX., CE = PWD = VIH VCC = VCC MAX., CE = PWD = Vcc 0.2 V PWD = GND 0.2 IOUT (RY /BY ) = 0 mA VCC = VCC MAX., CE = GND f = 8 MHz, IOUT = 0 mA CMOS Inputs
1 1
ICCS
VCC Standby Current
1, 3
30 0.20
ICCD
VCC Deep Power Down Current
1
20 ICCR VCC Read Current 25
35.0
mA
1 50.0 mA VCC = VCC MAX., CE = VIL f = 8 MHz, IOUT = 0 mA TTL Inputs
16
8M (1M x 8) Flash Memory
LH28F008SA
DC Characteristics (Continued)
SYMBOL PARAMETER TYP. MIN. MAX. UNITS TEST CONDITIONS NOTE
ICCW ICCE ICCES
VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current
10 10 5 1
30 30 10 10 200 5.0 30 30 200 -0.5 2.0 0.8 VCC + 0.5 0.45 2.4 0.0 6.5 12.6
mA mA mA A A A mA mA A V V V V V V V
Byte Write in Progress Block Erase in Progress Block Erase Suspended CE = VIH VPP VCC VPP VCC PWD = GND 0.2 V VPP = VPPH Byte Write in Progress VPP = VPPH, Block Erase in Progress VPP = VPPH, Block Erase Suspended
1 1 1, 2
IPPS IPPD IPPW IPPE IPPES VIL VIH VOL VOH VPPL VPPH VLKO
VPP Standby Current VPP Deep Power Down Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPP during Normal Operations VPP during Write/Erase Operations VCC Erase/Write Lock Voltage
1 1 1 1 1
90 0.10 10 10 90
VCC = VCC MIN. IOL = 5.8 mA VCC = VCC MIN. IOL = 2.5 mA
3 3 4
12
11.4 2.0
Capacitance5
TA = 25C, f = 1MHz
SYMBOL PARAMETER TYP. MAX. UNITS TEST CONDITIONS
CIN COUT
Input Capacitance Output Capacitance
6 8
8 12
pF pF
VIN = 0 V VIN = 0 V
NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, T = 25C. These currents are valid for all product versions (package and speeds). 2. ICCES is specified with the device deseleted. If the LH28F008SA is read while in Erase Suspend Mode, current draw is the sum of ICCES and ICCR. 3. Includes RY/BY. 4. Block Erases/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between V PPH and VPPL. 5. Sampled, not 100% tested.
17
LH28F008SA
8M (1M x 8) Flash Memory
AC INPUT/OUTPUT REFERENCE WAVEFORM1
2.4 INPUT 0.45 2.0 0.8 2.0 0.8
HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM2
3.0
TEST POINTS
OUTPUT
0.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
NOTE: AC test inputs are driven at VOH (2.4 VTTL) for a Logic '1' and VOL (0.45 VTTL) for a Logic '0.' Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
NOTE: AC test inputs are driven at 3.0 V for a Logic '1' and 0.0 V for a Logic '0'. Input timing begins, and output timing ends at 1.5 V. Input rise and fall times (10% to 90%) < 10 ns. 28F008SA-9
28F008SA-8
AC TESTING LOAD CIRCUIT1
1.3 V 1N914
HIGH SPEED AC TESTING LOAD CIRCUIT2
1.3 V 1N914
RL DEVICE UNDER TEST CL OUT DEVICE UNDER TEST
RL OUT CL
NOTE: CL = 100 pF CL Includes Jig Capacitance RL = 3.3 k
28F008SA-10
NOTE: CL = 30 pF CL Includes Jig Capacitance RL = 3.3 k
28F008SA-11
NOTES: 1. Testing characteristics for LH28F008SA-85 in Standard configuration, and LH28F008SA-12. 2. Testing characteristics for LH28F008SA-85 in High Speed configuration
18
8M (1M x 8) Flash Memory
LH28F008SA
AC CHARACTERISTICS - Read Only Operations1
SYMBOL PARAMETER LH28F008SA-854 LH28F008SA-855 LH28F008SA-125 VCC 5% VCC 10% VCC 10% MIN. MAX. MIN. MAX. MIN. MAX. UNIT NOTE
tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ
tAC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH
Read Cycle Time Address to Output Delay CE to Output Delay PWD High to Output Delay OE to Output Delay CE to Output Low Z CE High to Output High Z OE to Output Low Z OE High to Output High Z Output Hold from Addresses, CE or OE change, whichever is first
85 85 85 400 40 0 55 0 30 0
90 90 90 400 45 0 55 0 30 0
120 120 120 400 50 0 55 0 30 0
ns ns ns ns ns ns ns ns ns ns 2 3 3 3 3 3 2
NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load circuits for testing characteristics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
19
LH28F008SA
8M (1M x 8) Flash Memory
VCC POWER-UP
DEVICE AND ADDRESS STANDBY SELECTION
OUTPUTS ENABLED
DATA VALID
ADDRESSES (A)
VIH VIL
... ...
VCC STANDBY POWER-DOWN
ADDRESSES STABLE tAVAV
CE (E)
VIH VIL
...
tEHQZ
OE (G)
VIH VIL
...
tGHQZ
WE (W)
VIH VIL tGLQV tELQV tGLQX tELQX VOH VOL tAVQV 5.0 V GND tPHQV VIH VIL
28F008SA-12
tOH
DATA (D/Q)
HIGH-Z
VALID OUTPUT
... ...
HIGH-Z
VCC
PWD (P)
Figure 8. AC Waveform for Read Operations
20
8M (1M x 8) Flash Memory
LH28F008SA
AC CHARACTERISTICS - Write Operations1
LH28F008SA-857 LH28F008SA-858 LH28F008SA-128 VCC 5% VCC 10% VCC 10% MIN. MAX. MIN. MAX. MIN. MAX.
SYMBOL
PARAMETER
UNIT
NOTE
tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL
tWC tPS tCS tWP tVPS tAS tOS tDH tAH tOH
Write Cycle Time PWD High Recovery to WE Going Low CE Setup to WE Going Low WE Pulse Width VPP Setup to WE Going High Address Setup to WE Going High Data Setup to WE Going High Data Hold from WE High Address Hold from WE High OE Hold from WE High
85 1 10 40 100 40 40 5 5 10 30 100 6 0.3 0 0
90 1 10 40 100 40 40 5 5 10 30 100 6 0.3 0 0
120 1 10 40 100 40 40 5 5 10 30 100 6 0.3 0 0
ns s ns ns ns ns ns ns ns ns ns ns s s s ns 2 3 2
4
tWHP WE Pulse Width High WE High to RY /BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY /BY High
NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Command Definitions Table for Valid AIN for byte write or block erasure. 4. Refer to Command Definitions Table for valid DIN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measure to completion (SR.7 = 1. RY/BY = VOH). VPP should be held at VPPH until determina tion of byte write/block erase success (SR.3/4/5 = 0). 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
21
LH28F008SA
8M (1M x 8) Flash Memory
BLOCK ERASE AND BYTE WRITE PERFORMANCE
LH28F008SA-85 PARAMETER TYP.1 MIN. MAX. LH28F008SA-12 TYP.1 UNIT MIN. MAX. NOTE
Block Erase Time Block Write Time
1.6 0.6
10 2.1
1.6 0.6
10 2.1
s s
2 2
NOTES: 1. 25C, 12.0 VPP. 2. Excludes System-Level Overhead.
VCC POWER-UP AND STANDBY
WRITE BYTE WRITE OR ERASE SETUP COMMAND
WRITE VALID ADDRESS AND DATA (BYTE WRITE) OR ERASE CONFIRM COMMAND
AUTOMATED BYTE WRITE OR ERASE DELAY
READ STATUS REGISTER DATA
WRITE READ ARRAY COMMAND
ADDRESSES (A)
VIH VIL
AIN tAVAV tAVWH
AIN tWHAX
CE (E)
VIH VIL tELWL tWHEH tWHGL
OE (G)
VIH VIL tWHWL VIH VIL tWLWH tDVWH tWHDX tWHQV1, 2
WE (W)
DATA (D/Q)
VIH VIL
HIGH-Z tPHWL
DIN
DIN tWHRL
VALID SRD
DIN
RY/BY (R)
VOH VOL VIH VIL tVPWH tQVVL
PWD (P)
VPPH VPPL VPP (V) V IH VIL
28F008SA-13
Figure 9. AC Waveform for Write Operations
22
8M (1M x 8) Flash Memory
LH28F008SA
ALTERNATIVE CE - CONTROLLED WRITES
SYMBOL PARAMETER LH28F008SA-856 LH28F008SA-857 LH28F008SA-127 VCC 5% VCC 10% VCC 10% MIN. MAX. MIN. MAX. MIN. MAX. UNIT NOTE
tAVAV tPHEL tWLEL tELEH tVPEH tAVEH
tDVEH
tWC tPS tWS tCP
Write Cycle Time PWD High Recovery to CE Going Low WE Setup to CE Going Low CE Pulse Width
85 1 0 50 100 40 40 5 5 0 25 100 6 0.3 0 0
90 1 0 50 100 40 40 5 5 0 25 100 6 0.3 0 0
120 1 0 50 100 40 40 5 5 0 25 100 6 0.3 0 0
ns s ns ns ns ns ns ns ns ns ns ns s s s ns 2, 5 5 5 2 3 4 2
tVPS VPP Setup to CE Going High tAS tDS tDH tAH tWH Address Setup to CE Going High Data Setup to CE Going High Data Hold from CE High Address Hold from CE High WE Hold from CE High
tEHDX tEHAX tEHWH tEHEL tEHRL tEHOV1 tEHOV2 tEHGL tQVVL
tEPH CE Pulse Width High CE High to RY /BY Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY /BY High
NOTE: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combinations of CE and WE. In systems where CE defines the write pulsewidth (within a longer WE timing waveform), all setup, hold and inactive WE times should be measured relative to the CE waveform. 2. Sampled, not 100% tested. 3. Refer to Command Definitions Table for valid AIN for byte write or block erasure. 4. Refer to Command Definitions Table for valid DIN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0). 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
23
LH28F008SA
8M (1M x 8) Flash Memory
VCC POWER-UP AND STANDBY
WRITE BYTE WRITE OR ERASE SETUP COMMAND
WRITE VALID ADDRESS AND DATA (BYTE WRITE) OR ERASE CONFIRM COMMAND
AUTOMATED BYTE WRITE OR ERASE DELAY
READ STATUS REGISTER DATA
WRITE READ ARRAY COMMAND
ADDRESSES (A)
VIH VIL
AIN tAVAV
AIN tAVEH tEHAX
WE (W)
VIH VIL
tWLEL tEHWH
tEHGL
OE (G)
VIH VIL tEHEL VIH VIL tELEH tDVEH tEHDX tEHQV1, 2
CE (E)
DATA (D/Q)
VIH VIL
HIGH-Z tPHEL
DIN
DIN tEHRL
VALID SRD
DIN
RY/BY (R)
VOH VOL VIH VIL tVPEH tQVVL
PWD (P)
VPPH VPPL VPP (V) V IH VIL
28F008SA-14
Figure 10. Alternate AC Waveform for Write Operations
24
8M (1M x 8) Flash Memory
LH28F008SA
44SOP (SOP044-P-0600)
1.27 [0.050] TYP.
0.50 [0.020] 0.30 [0.012]
44
23
13.40 [0.528] 13.00 [0.512]
16.40 [0.646] 15.60 [0.614]
14.40 [0.567]
1 28.40 [1.118] 28.00 [1.102]
22
SEE DETAIL 0.20 [0.008] 0.10 [0.004] 2.9 [0.114] 2.5 [0.098]
DETAIL
0.15 [0.006] 1.275 [0.050] 2.9 [0.114] 2.5 [0.098] 0.25 [0.010] 0.05 [0.002] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 3.25 [0.128] 2.45 [0.096] 0.25 [0.010] 0.05 [0.002]
1.275 [0.050]
0 - 10 0.80 [0.031]
44SOP
25
LH28F008SA
8M (1M x 8) Flash Memory
40TSOP (TSOP040-P-1020)
1 40
0.50 [0.020] TYP. 0.25 [0.010] 0.15 [0.006]
10.20 [0.402] 9.80 [0.386]
20
21
1.10 [0.043] 0.90 [0.035] SEE DETAIL 1.19 [0.047] MAX. 0.49 [0.019] 0.39 [0.015]
DETAIL
0.125 [0.005] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] 20.30 [0.799] 19.70 [0.776] MAXIMUM LIMIT MINIMUM LIMIT 0.49 [0.019] 0.39 [0.015] 0.22 [0.009] 0.02 [0.001]
0 - 10 0.18 [0.007] 0.08 [0.003]
40TSOP
DIMENSIONS IN MM [INCHES]
ORDERING INFORMATION
LH28F008SA Device Type X Package -## Speed 85 85 12 120 Access Time (ns) T 40-pin, 1.2 mm x 10 mm x 20 mm TSOP (Type I) (TSOP040-P-1020) N 44-pin, 600-mil SOP (SOP044-P-0600) 8M (1M x 8) Flash Memory Example: LH28F008SAT-85 (8M (1M x 8) Flash Memory, 85 ns, 40-pin TSOP)
28F008SA-15
26
8M (1M x 8) Flash Memory
LH28F008SA
LIFE SUPPORT POLICY SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation. WARRANTY SHARP warrants to Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, SHARP will refund the purchase price of the Product upon its return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than SHARP. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE ARE SPECIFICALLY EXCLUDED. SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.
(R)
NORTH AMERICA
EUROPE
ASIA
SHARP Electronics Corporation Microelectronics Group 5700 NW Pacific Rim Blvd., M/S 20 Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Telex: LABOMETA-B J63428 Facsimile: (07436) 5-1532
(c)1997 by SHARP Corporation Issued July 1994
Reference Code SMT96105

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Price & Availability of LH28F008SA

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